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High-Level Synthesis

Papers

Showing 8190 of 96 papers

TitleStatusHype
Pyramid: Machine Learning Framework to Estimate the Optimal Timing and Resource Usage of a High-Level Synthesis Design0
Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis0
Software-Defined FPGA Accelerator Design for Mobile Deep Learning Applications0
AutoPhase: Compiler Phase-Ordering for High Level Synthesis with Deep Reinforcement LearningCode1
Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAsCode0
FPGA-Based CNN Inference Accelerator Synthesized from Multi-Threaded C Software0
Real-time on-board obstacle avoidance for UAVs based on embedded stereo vision0
LeFlow: Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural NetworksCode1
On the Resilience of RTL NN Accelerators: Fault Characterization and Mitigation0
SqueezeJet: High-level Synthesis Accelerator Design for Deep Convolutional Neural Networks0
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