| AutoHLS: Learning to Accelerate Design Space Exploration for HLS Designs | Mar 15, 2024 | Bayesian OptimizationHigh-Level Synthesis | —Unverified | 0 |
| Subgraph Extraction-based Feedback-guided Iterative Scheduling for HLS | Jan 22, 2024 | High-Level SynthesisScheduling | —Unverified | 0 |
| A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures | Nov 29, 2023 | Deep LearningHigh-Level Synthesis | —Unverified | 0 |
| Leveraging High-Level Synthesis and Large Language Models to Generate, Simulate, and Deploy a Uniform Random Number Generator Hardware Design | Nov 6, 2023 | High-Level SynthesisLanguage Modeling | —Unverified | 0 |
| Implementation of hyperspectral inversion algorithms on FPGA: Hardware comparison using High Level Synthesis | Oct 3, 2023 | High-Level Synthesis | —Unverified | 0 |
| SEER: Super-Optimization Explorer for HLS using E-graph Rewriting with MLIR | Aug 15, 2023 | High-Level Synthesis | —Unverified | 0 |
| INR-Arch: A Dataflow Architecture and Compiler for Arbitrary-Order Gradient Computations in Implicit Neural Representation Processing | Aug 11, 2023 | CPUGPU | CodeCode Available | 0 |
| ProgSG: Cross-Modality Representation Learning for Programs in Electronic Design Automation | May 18, 2023 | Autonomous DrivingHigh-Level Synthesis | —Unverified | 0 |
| DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators | Mar 14, 2023 | High-Level Synthesis | —Unverified | 0 |
| HLSDataset: Open-Source Dataset for ML-Assisted FPGA Design using High Level Synthesis | Feb 17, 2023 | High-Level Synthesis | CodeCode Available | 0 |
