| Leveraging High-Level Synthesis and Large Language Models to Generate, Simulate, and Deploy a Uniform Random Number Generator Hardware Design | Nov 6, 2023 | High-Level SynthesisLanguage Modeling | —Unverified | 0 |
| Implementation of hyperspectral inversion algorithms on FPGA: Hardware comparison using High Level Synthesis | Oct 3, 2023 | High-Level Synthesis | —Unverified | 0 |
| GNNHLS: Evaluating Graph Neural Network Inference via High-Level Synthesis | Sep 27, 2023 | CPUGPU | CodeCode Available | 1 |
| Towards a Comprehensive Benchmark for High-Level Synthesis Targeted to FPGAs | Sep 26, 2023 | High-Level Synthesis | CodeCode Available | 1 |
| SEER: Super-Optimization Explorer for HLS using E-graph Rewriting with MLIR | Aug 15, 2023 | High-Level Synthesis | —Unverified | 0 |
| INR-Arch: A Dataflow Architecture and Compiler for Arbitrary-Order Gradient Computations in Implicit Neural Representation Processing | Aug 11, 2023 | CPUGPU | CodeCode Available | 0 |
| Edge-MoE: Memory-Efficient Multi-Task Vision Transformer Architecture with Task-level Sparsity via Mixture-of-Experts | May 30, 2023 | CPUGPU | CodeCode Available | 1 |
| ProgSG: Cross-Modality Representation Learning for Programs in Electronic Design Automation | May 18, 2023 | Autonomous DrivingHigh-Level Synthesis | —Unverified | 0 |
| DGNN-Booster: A Generic FPGA Accelerator Framework For Dynamic Graph Neural Network Inference | Apr 13, 2023 | CPUGPU | CodeCode Available | 1 |
| DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators | Mar 14, 2023 | High-Level Synthesis | —Unverified | 0 |
