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High-Level Synthesis

Papers

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Showing 76–96 of 96 papers

TitleStatusHype
Implementation of hyperspectral inversion algorithms on FPGA: Hardware comparison using High Level Synthesis—0
Intelligent4DSE: Optimizing High-Level Synthesis Design Space Exploration with Graph Neural Networks and Large Language Models—0
Intelligent experiments through real-time AI: Fast Data Processing and Autonomous Detector Control for sPHENIX and future EIC detectors—0
HLSDataset: Open-Source Dataset for ML-Assisted FPGA Design using High Level SynthesisCode0
Hierarchical Mixture of Experts: Generalizable Learning for High-Level SynthesisCode0
Hardware-Efficient Deconvolution-Based GAN for Edge ComputingCode0
Iceberg: Enhancing HLS Modeling with Synthetic DataCode0
Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAsCode0
CuFP: An HLS Library for Customized Floating-Point OperatorsCode0
INR-Arch: A Dataflow Architecture and Compiler for Arbitrary-Order Gradient Computations in Implicit Neural Representation ProcessingCode0
Skip the Benchmark: Generating System-Level High-Level Synthesis Data using Generative Machine LearningCode0
Enhancing CuFP Library with Self-Alignment TechniqueCode0
Agentic-HLS: An agentic reasoning based high-level synthesis system using large language models (AI for EDA workshop 2024)Code0
Accelerated Charged Particle Tracking with Graph Neural Networks on FPGAsCode0
Learning to Compare Hardware Designs for High-Level SynthesisCode0
fSEAD: a Composable FPGA-based Streaming Ensemble Anomaly Detection LibraryCode0
ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural NetworkCode0
Fast Algorithms for Spiking Neural Network Simulation with FPGAsCode0
Exploring the Limitations of Kolmogorov-Arnold Networks in Classification: Insights to Software Training and Hardware ImplementationCode0
Deep Inverse Design for High-Level SynthesisCode0
Neural Architecture Codesign for Fast Physics ApplicationsCode0
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