SOTAVerified

High-Level Synthesis

Papers

Recently AddedMost HypedMost ActiveNeeds VerificationMost Verified

Showing 51–75 of 96 papers

TitleStatusHype
Data-Driven Background Subtraction Algorithm for in-Camera Acceleration in Thermal Imagery—0
DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators—0
Efficient Compilation and Mapping of Fixed Function Combinational Logic onto Digital Signal Processors Targeting Neural Network Inference and Utilizing High-level Synthesis—0
Efficient Task Transfer for HLS DSE—0
Embedded FPGA Acceleration of Brain-Like Neural Networks: Online Learning to Scalable Inference—0
Embeddings in Natural Language Processing—0
IronMan: GNN-assisted Design Space Exploration in High-Level Synthesis via Reinforcement Learning—0
KALAM: toolKit for Automating high-Level synthesis of Analog computing systeMs—0
Leveraging High-Level Synthesis and Large Language Models to Generate, Simulate, and Deploy a Uniform Random Number Generator Hardware Design—0
MetaML-Pro: Cross-Stage Design Flow Automation for Efficient Deep Learning Acceleration—0
New Solutions on LLM Acceleration, Optimization, and Application—0
On the Resilience of RTL NN Accelerators: Fault Characterization and Mitigation—0
OpenHLS: High-Level Synthesis for Low-Latency Deep Neural Networks for Experimental Science—0
ProgSG: Cross-Modality Representation Learning for Programs in Electronic Design Automation—0
Pyramid: Machine Learning Framework to Estimate the Optimal Timing and Resource Usage of a High-Level Synthesis Design—0
Real-time on-board obstacle avoidance for UAVs based on embedded stereo vision—0
SEER: Super-Optimization Explorer for HLS using E-graph Rewriting with MLIR—0
Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis—0
Software-Defined FPGA Accelerator Design for Mobile Deep Learning Applications—0
SqueezeJet: High-level Synthesis Accelerator Design for Deep Convolutional Neural Networks—0
Subgraph Extraction-based Feedback-guided Iterative Scheduling for HLS—0
High-level synthesis design of scalable ultrafast ultrasound beamformer with single FPGA—0
Towards Enabling Dynamic Convolution Neural Network Inference for Edge Intelligence—0
VAQF: Fully Automatic Software-Hardware Co-Design Framework for Low-Bit Vision Transformer—0
iDSE: Navigating Design Space Exploration in High-Level Synthesis Using LLMs—0
Show:102550
← PrevPage 3 of 4Next →

No leaderboard results yet.