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High-Level Synthesis

Papers

Showing 21–30 of 96 papers

TitleStatusHype
PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNsCode1
LeFlow: Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural NetworksCode1
A scalable and efficient convolutional neural network accelerator using HLS for a System on Chip designCode1
AutoHLS: Learning to Accelerate Design Space Exploration for HLS Designs—0
A system on chip for melanoma detection using FPGA-based SVM classifier—0
Accelerating Markov Random Field Inference with Uncertainty Quantification—0
Efficient Compilation and Mapping of Fixed Function Combinational Logic onto Digital Signal Processors Targeting Neural Network Inference and Utilizing High-level Synthesis—0
DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators—0
Data-Driven Background Subtraction Algorithm for in-Camera Acceleration in Thermal Imagery—0
A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures—0
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