SOTAVerified

High-Level Synthesis

Papers

Showing 2130 of 96 papers

TitleStatusHype
PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNsCode1
LeFlow: Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural NetworksCode1
A scalable and efficient convolutional neural network accelerator using HLS for a System on Chip designCode1
AutoHLS: Learning to Accelerate Design Space Exploration for HLS Designs0
A system on chip for melanoma detection using FPGA-based SVM classifier0
Accelerating Markov Random Field Inference with Uncertainty Quantification0
Efficient Compilation and Mapping of Fixed Function Combinational Logic onto Digital Signal Processors Targeting Neural Network Inference and Utilizing High-level Synthesis0
DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators0
Data-Driven Background Subtraction Algorithm for in-Camera Acceleration in Thermal Imagery0
A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures0
Show:102550
← PrevPage 3 of 10Next →

No leaderboard results yet.