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High-Level Synthesis

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Showing 51–96 of 96 papers

TitleStatusHype
SqueezeJet: High-level Synthesis Accelerator Design for Deep Convolutional Neural Networks—0
Subgraph Extraction-based Feedback-guided Iterative Scheduling for HLS—0
High-level synthesis design of scalable ultrafast ultrasound beamformer with single FPGA—0
Towards Enabling Dynamic Convolution Neural Network Inference for Edge Intelligence—0
VAQF: Fully Automatic Software-Hardware Co-Design Framework for Low-Bit Vision Transformer—0
iDSE: Navigating Design Space Exploration in High-Level Synthesis Using LLMs—0
Accelerating Markov Random Field Inference with Uncertainty Quantification—0
A Compilation Flow for the Generation of CNN Inference Accelerators on FPGAs—0
A Graph Deep Learning Framework for High-Level Synthesis Design Space Exploration—0
A reconfigurable neural network ASIC for detector front-end data compression at the HL-LHC—0
A Reconfigurable Stream-Based FPGA Accelerator for Bayesian Confidence Propagation Neural Networks—0
Are LLMs Any Good for High-Level Synthesis?—0
A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures—0
A system on chip for melanoma detection using FPGA-based SVM classifier—0
AutoHLS: Learning to Accelerate Design Space Exploration for HLS Designs—0
Automated C/C++ Program Repair for High-Level Synthesis via Large Language Models—0
Automatic Optimization of Hardware Accelerators for Image Processing—0
Brain-Inspired Deep Networks for Image Aesthetics Assessment—0
Can Reasoning Models Reason about Hardware? An Agentic HLS Perspective—0
Chimera: A Hybrid Machine Learning Driven Multi-Objective Design Space Exploration Tool for FPGA High-Level Synthesis—0
Code Generation for High-Level Synthesis of Multiresolution Applications on FPGAs—0
Cross-Modality Program Representation Learning for Electronic Design Automation with High-Level Synthesis—0
Data-Driven Background Subtraction Algorithm for in-Camera Acceleration in Thermal Imagery—0
DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators—0
Efficient Compilation and Mapping of Fixed Function Combinational Logic onto Digital Signal Processors Targeting Neural Network Inference and Utilizing High-level Synthesis—0
Efficient Task Transfer for HLS DSE—0
Embedded FPGA Acceleration of Brain-Like Neural Networks: Online Learning to Scalable Inference—0
Embeddings in Natural Language Processing—0
Exploring Code Language Models for Automated HLS-based Hardware Generation: Benchmark, Infrastructure and Analysis—0
Face Recognition with Hybrid Efficient Convolution Algorithms on FPGAs—0
FFCNN: Fast FPGA based Acceleration for Convolution neural network inference—0
Firmware implementation of a recurrent neural network for the computation of the energy deposited in the liquid argon calorimeter of the ATLAS experiment—0
FPGA-Based CNN Inference Accelerator Synthesized from Multi-Threaded C Software—0
FPGA-Based Hardware Accelerator of Homomorphic Encryption for Efficient Federated Learning—0
Enabling Automated FPGA Accelerator Optimization Using Graph Neural Networks—0
Gradient Backpropagation based Feature Attribution to Enable Explainable-AI on the Edge—0
HENNC: Hardware Engine for Artificial Neural Network-based Chaotic Oscillators—0
High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing—0
Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis—0
Implementation of hyperspectral inversion algorithms on FPGA: Hardware comparison using High Level Synthesis—0
Intelligent4DSE: Optimizing High-Level Synthesis Design Space Exploration with Graph Neural Networks and Large Language Models—0
Intelligent experiments through real-time AI: Fast Data Processing and Autonomous Detector Control for sPHENIX and future EIC detectors—0
IronMan: GNN-assisted Design Space Exploration in High-Level Synthesis via Reinforcement Learning—0
KALAM: toolKit for Automating high-Level synthesis of Analog computing systeMs—0
Leveraging High-Level Synthesis and Large Language Models to Generate, Simulate, and Deploy a Uniform Random Number Generator Hardware Design—0
MetaML-Pro: Cross-Stage Design Flow Automation for Efficient Deep Learning Acceleration—0
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