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High-Level Synthesis

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Showing 51–96 of 96 papers

TitleStatusHype
AutoHLS: Learning to Accelerate Design Space Exploration for HLS Designs—0
Subgraph Extraction-based Feedback-guided Iterative Scheduling for HLS—0
A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures—0
Leveraging High-Level Synthesis and Large Language Models to Generate, Simulate, and Deploy a Uniform Random Number Generator Hardware Design—0
Implementation of hyperspectral inversion algorithms on FPGA: Hardware comparison using High Level Synthesis—0
SEER: Super-Optimization Explorer for HLS using E-graph Rewriting with MLIR—0
INR-Arch: A Dataflow Architecture and Compiler for Arbitrary-Order Gradient Computations in Implicit Neural Representation ProcessingCode0
ProgSG: Cross-Modality Representation Learning for Programs in Electronic Design Automation—0
DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators—0
HLSDataset: Open-Source Dataset for ML-Assisted FPGA Design using High Level SynthesisCode0
Firmware implementation of a recurrent neural network for the computation of the energy deposited in the liquid argon calorimeter of the ATLAS experiment—0
OpenHLS: High-Level Synthesis for Low-Latency Deep Neural Networks for Experimental Science—0
Sensor Signal Processing using High-Level Synthesis and Internet of Things with a Layered Architecture—0
Gradient Backpropagation based Feature Attribution to Enable Explainable-AI on the Edge—0
FFCNN: Fast FPGA based Acceleration for Convolution neural network inference—0
High-level synthesis design of scalable ultrafast ultrasound beamformer with single FPGA—0
Efficient Compilation and Mapping of Fixed Function Combinational Logic onto Digital Signal Processors Targeting Neural Network Inference and Utilizing High-level Synthesis—0
Chimera: A Hybrid Machine Learning Driven Multi-Objective Design Space Exploration Tool for FPGA High-Level Synthesis—0
A Compilation Flow for the Generation of CNN Inference Accelerators on FPGAs—0
Towards Enabling Dynamic Convolution Neural Network Inference for Edge Intelligence—0
High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing—0
Hardware-Efficient Deconvolution-Based GAN for Edge ComputingCode0
VAQF: Fully Automatic Software-Hardware Co-Design Framework for Low-Bit Vision Transformer—0
A Graph Deep Learning Framework for High-Level Synthesis Design Space Exploration—0
Enabling Automated FPGA Accelerator Optimization Using Graph Neural Networks—0
A system on chip for melanoma detection using FPGA-based SVM classifier—0
Accelerating Markov Random Field Inference with Uncertainty Quantification—0
A reconfigurable neural network ASIC for detector front-end data compression at the HL-LHC—0
IronMan: GNN-assisted Design Space Exploration in High-Level Synthesis via Reinforcement Learning—0
Embeddings in Natural Language Processing—0
Accelerated Charged Particle Tracking with Graph Neural Networks on FPGAsCode0
FPGA-Based Hardware Accelerator of Homomorphic Encryption for Efficient Federated Learning—0
ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural NetworkCode0
Pyramid: Machine Learning Framework to Estimate the Optimal Timing and Resource Usage of a High-Level Synthesis Design—0
Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis—0
Software-Defined FPGA Accelerator Design for Mobile Deep Learning Applications—0
Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAsCode0
FPGA-Based CNN Inference Accelerator Synthesized from Multi-Threaded C Software—0
Real-time on-board obstacle avoidance for UAVs based on embedded stereo vision—0
On the Resilience of RTL NN Accelerators: Fault Characterization and Mitigation—0
SqueezeJet: High-level Synthesis Accelerator Design for Deep Convolutional Neural Networks—0
Face Recognition with Hybrid Efficient Convolution Algorithms on FPGAs—0
Data-Driven Background Subtraction Algorithm for in-Camera Acceleration in Thermal Imagery—0
Brain-Inspired Deep Networks for Image Aesthetics Assessment—0
Automatic Optimization of Hardware Accelerators for Image Processing—0
Code Generation for High-Level Synthesis of Multiresolution Applications on FPGAs—0
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