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High-Level Synthesis

Papers

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Showing 26–50 of 96 papers

TitleStatusHype
Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAsCode0
Enhancing CuFP Library with Self-Alignment TechniqueCode0
Agentic-HLS: An agentic reasoning based high-level synthesis system using large language models (AI for EDA workshop 2024)Code0
Exploring the Limitations of Kolmogorov-Arnold Networks in Classification: Insights to Software Training and Hardware ImplementationCode0
CuFP: An HLS Library for Customized Floating-Point OperatorsCode0
Learning to Compare Hardware Designs for High-Level SynthesisCode0
Accelerated Charged Particle Tracking with Graph Neural Networks on FPGAsCode0
Fast Algorithms for Spiking Neural Network Simulation with FPGAsCode0
Iceberg: Enhancing HLS Modeling with Synthetic DataCode0
Hierarchical Mixture of Experts: Generalizable Learning for High-Level SynthesisCode0
INR-Arch: A Dataflow Architecture and Compiler for Arbitrary-Order Gradient Computations in Implicit Neural Representation ProcessingCode0
Neural Architecture Codesign for Fast Physics ApplicationsCode0
Skip the Benchmark: Generating System-Level High-Level Synthesis Data using Generative Machine LearningCode0
HLSDataset: Open-Source Dataset for ML-Assisted FPGA Design using High Level SynthesisCode0
Deep Inverse Design for High-Level SynthesisCode0
Hardware-Efficient Deconvolution-Based GAN for Edge ComputingCode0
New Solutions on LLM Acceleration, Optimization, and Application—0
On the Resilience of RTL NN Accelerators: Fault Characterization and Mitigation—0
OpenHLS: High-Level Synthesis for Low-Latency Deep Neural Networks for Experimental Science—0
ProgSG: Cross-Modality Representation Learning for Programs in Electronic Design Automation—0
Pyramid: Machine Learning Framework to Estimate the Optimal Timing and Resource Usage of a High-Level Synthesis Design—0
Real-time on-board obstacle avoidance for UAVs based on embedded stereo vision—0
SEER: Super-Optimization Explorer for HLS using E-graph Rewriting with MLIR—0
Sensor Signal Processing using High-Level Synthesis and Internet of Things with a Layered Architecture—0
Software-Defined FPGA Accelerator Design for Mobile Deep Learning Applications—0
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