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High-Level Synthesis

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Showing 26–50 of 96 papers

TitleStatusHype
Automated C/C++ Program Repair for High-Level Synthesis via Large Language Models—0
New Solutions on LLM Acceleration, Optimization, and Application—0
Cross-Modality Program Representation Learning for Electronic Design Automation with High-Level Synthesis—0
fSEAD: a Composable FPGA-based Streaming Ensemble Anomaly Detection LibraryCode0
SynthAI: A Multi Agent Generative AI Framework for Automated Modular HLS Design GenerationCode1
Fast Algorithms for Spiking Neural Network Simulation with FPGAsCode0
HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and BeyondCode2
HLSTransform: Energy-Efficient Llama 2 Inference on FPGAs Via High Level SynthesisCode2
Skip the Benchmark: Generating System-Level High-Level Synthesis Data using Generative Machine LearningCode0
Allo: A Programming Model for Composable Accelerator DesignCode3
AutoHLS: Learning to Accelerate Design Space Exploration for HLS Designs—0
Subgraph Extraction-based Feedback-guided Iterative Scheduling for HLS—0
Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNsCode1
Understanding the Potential of FPGA-Based Spatial Acceleration for Large Language Model InferenceCode2
A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures—0
Leveraging High-Level Synthesis and Large Language Models to Generate, Simulate, and Deploy a Uniform Random Number Generator Hardware Design—0
Implementation of hyperspectral inversion algorithms on FPGA: Hardware comparison using High Level Synthesis—0
GNNHLS: Evaluating Graph Neural Network Inference via High-Level SynthesisCode1
Towards a Comprehensive Benchmark for High-Level Synthesis Targeted to FPGAsCode1
SEER: Super-Optimization Explorer for HLS using E-graph Rewriting with MLIR—0
INR-Arch: A Dataflow Architecture and Compiler for Arbitrary-Order Gradient Computations in Implicit Neural Representation ProcessingCode0
Edge-MoE: Memory-Efficient Multi-Task Vision Transformer Architecture with Task-level Sparsity via Mixture-of-ExpertsCode1
ProgSG: Cross-Modality Representation Learning for Programs in Electronic Design Automation—0
DGNN-Booster: A Generic FPGA Accelerator Framework For Dynamic Graph Neural Network InferenceCode1
DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators—0
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