| Allo: A Programming Model for Composable Accelerator Design | Apr 7, 2024 | GPUHigh-Level Synthesis | CodeCode Available | 3 | 5 |
| Understanding the Potential of FPGA-Based Spatial Acceleration for Large Language Model Inference | Dec 23, 2023 | GPUHigh-Level Synthesis | CodeCode Available | 2 | 5 |
| HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond | May 1, 2024 | BenchmarkingHigh-Level Synthesis | CodeCode Available | 2 | 5 |
| Fast inference of deep neural networks in FPGAs for particle physics | Apr 16, 2018 | BIG-bench Machine LearningHigh-Level Synthesis | CodeCode Available | 2 | 5 |
| HLSTransform: Energy-Efficient Llama 2 Inference on FPGAs Via High Level Synthesis | Apr 29, 2024 | CPUEdge-computing | CodeCode Available | 2 | 5 |
| Edge-MoE: Memory-Efficient Multi-Task Vision Transformer Architecture with Task-level Sparsity via Mixture-of-Experts | May 30, 2023 | CPUGPU | CodeCode Available | 1 | 5 |
| HLS-Eval: A Benchmark and Framework for Evaluating LLMs on High-Level Synthesis Design Tasks | Apr 16, 2025 | High-Level SynthesisLarge Language Model | CodeCode Available | 1 | 5 |
| A scalable and efficient convolutional neural network accelerator using HLS for a System on Chip design | Apr 27, 2020 | High-Level Synthesis | CodeCode Available | 1 | 5 |
| LeFlow: Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks | Jul 14, 2018 | BIG-bench Machine LearningHigh-Level Synthesis | CodeCode Available | 1 | 5 |
| LL-GNN: Low Latency Graph Neural Networks on FPGAs for High Energy Physics | Sep 28, 2022 | GPUGraph Neural Network | CodeCode Available | 1 | 5 |
| LLM-DSE: Searching Accelerator Parameters with LLM Agents | May 18, 2025 | High-Level Synthesis | CodeCode Available | 1 | 5 |
| AutoPhase: Compiler Phase-Ordering for High Level Synthesis with Deep Reinforcement Learning | Jan 15, 2019 | Deep Reinforcement LearningHigh-Level Synthesis | CodeCode Available | 1 | 5 |
| AutoPhase: Juggling HLS Phase Orderings in Random Forests with Deep Reinforcement Learning | Mar 2, 2020 | Deep Reinforcement LearningHigh-Level Synthesis | CodeCode Available | 1 | 5 |
| PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs | Jan 25, 2022 | graph constructionGraph Learning | CodeCode Available | 1 | 5 |
| Design and Implementation of an FPGA-Based Hardware Accelerator for Transformer | Mar 20, 2025 | CPUHigh-Level Synthesis | CodeCode Available | 1 | 5 |
| GenGNN: A Generic FPGA Framework for Graph Neural Network Acceleration | Jan 20, 2022 | CPUDrug Discovery | CodeCode Available | 1 | 5 |
| rule4ml: An Open-Source Tool for Resource Utilization and Latency Estimation for ML Models on FPGA | Aug 9, 2024 | High-Level Synthesis | CodeCode Available | 1 | 5 |
| DGNN-Booster: A Generic FPGA Accelerator Framework For Dynamic Graph Neural Network Inference | Apr 13, 2023 | CPUGPU | CodeCode Available | 1 | 5 |
| GNNHLS: Evaluating Graph Neural Network Inference via High-Level Synthesis | Sep 27, 2023 | CPUGPU | CodeCode Available | 1 | 5 |
| Accelerating Recurrent Neural Networks for Gravitational Wave Experiments | Jun 26, 2021 | High-Level SynthesisTime Series | CodeCode Available | 1 | 5 |
| SynthAI: A Multi Agent Generative AI Framework for Automated Modular HLS Design Generation | May 25, 2024 | High-Level SynthesisRAG | CodeCode Available | 1 | 5 |
| Towards a Comprehensive Benchmark for High-Level Synthesis Targeted to FPGAs | Sep 26, 2023 | High-Level Synthesis | CodeCode Available | 1 | 5 |
| Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs | Jan 14, 2024 | graph constructionHigh-Level Synthesis | CodeCode Available | 1 | 5 |
| ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network | May 14, 2020 | Autonomous VehiclesHigh-Level Synthesis | CodeCode Available | 0 | 5 |
| fSEAD: a Composable FPGA-based Streaming Ensemble Anomaly Detection Library | Jun 10, 2024 | Anomaly DetectionCPU | CodeCode Available | 0 | 5 |
| Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs | Nov 21, 2018 | High-Level Synthesis | CodeCode Available | 0 | 5 |
| Enhancing CuFP Library with Self-Alignment Technique | Mar 24, 2025 | High-Level Synthesis | CodeCode Available | 0 | 5 |
| Agentic-HLS: An agentic reasoning based high-level synthesis system using large language models (AI for EDA workshop 2024) | Dec 2, 2024 | BenchmarkingHigh-Level Synthesis | CodeCode Available | 0 | 5 |
| Exploring the Limitations of Kolmogorov-Arnold Networks in Classification: Insights to Software Training and Hardware Implementation | Jul 25, 2024 | High-Level SynthesisKolmogorov-Arnold Networks | CodeCode Available | 0 | 5 |
| CuFP: An HLS Library for Customized Floating-Point Operators | Jul 18, 2024 | High-Level Synthesis | CodeCode Available | 0 | 5 |
| Learning to Compare Hardware Designs for High-Level Synthesis | Sep 20, 2024 | High-Level Synthesis | CodeCode Available | 0 | 5 |
| Accelerated Charged Particle Tracking with Graph Neural Networks on FPGAs | Nov 30, 2020 | CPUHigh-Level Synthesis | CodeCode Available | 0 | 5 |
| Fast Algorithms for Spiking Neural Network Simulation with FPGAs | May 3, 2024 | GPUHigh-Level Synthesis | CodeCode Available | 0 | 5 |
| Iceberg: Enhancing HLS Modeling with Synthetic Data | Jul 14, 2025 | Data AugmentationHigh-Level Synthesis | CodeCode Available | 0 | 5 |
| Hierarchical Mixture of Experts: Generalizable Learning for High-Level Synthesis | Oct 25, 2024 | High-Level SynthesisMixture-of-Experts | CodeCode Available | 0 | 5 |
| INR-Arch: A Dataflow Architecture and Compiler for Arbitrary-Order Gradient Computations in Implicit Neural Representation Processing | Aug 11, 2023 | CPUGPU | CodeCode Available | 0 | 5 |
| Neural Architecture Codesign for Fast Physics Applications | Jan 9, 2025 | High-Level SynthesisModel Compression | CodeCode Available | 0 | 5 |
| Skip the Benchmark: Generating System-Level High-Level Synthesis Data using Generative Machine Learning | Apr 23, 2024 | Generative Adversarial NetworkHigh-Level Synthesis | CodeCode Available | 0 | 5 |
| HLSDataset: Open-Source Dataset for ML-Assisted FPGA Design using High Level Synthesis | Feb 17, 2023 | High-Level Synthesis | CodeCode Available | 0 | 5 |
| Deep Inverse Design for High-Level Synthesis | Jul 11, 2024 | High-Level Synthesis | CodeCode Available | 0 | 5 |
| Hardware-Efficient Deconvolution-Based GAN for Edge Computing | Jan 18, 2022 | Edge-computingHigh-Level Synthesis | CodeCode Available | 0 | 5 |
| New Solutions on LLM Acceleration, Optimization, and Application | Jun 16, 2024 | High-Level Synthesis | —Unverified | 0 | 0 |
| On the Resilience of RTL NN Accelerators: Fault Characterization and Mitigation | Jun 14, 2018 | High-Level Synthesis | —Unverified | 0 | 0 |
| OpenHLS: High-Level Synthesis for Low-Latency Deep Neural Networks for Experimental Science | Feb 13, 2023 | High-Level SynthesisLow-latency processing | —Unverified | 0 | 0 |
| ProgSG: Cross-Modality Representation Learning for Programs in Electronic Design Automation | May 18, 2023 | Autonomous DrivingHigh-Level Synthesis | —Unverified | 0 | 0 |
| Pyramid: Machine Learning Framework to Estimate the Optimal Timing and Resource Usage of a High-Level Synthesis Design | Jul 29, 2019 | High-Level Synthesis | —Unverified | 0 | 0 |
| Real-time on-board obstacle avoidance for UAVs based on embedded stereo vision | Jul 17, 2018 | Disparity EstimationHigh-Level Synthesis | —Unverified | 0 | 0 |
| SEER: Super-Optimization Explorer for HLS using E-graph Rewriting with MLIR | Aug 15, 2023 | High-Level Synthesis | —Unverified | 0 | 0 |
| Sensor Signal Processing using High-Level Synthesis and Internet of Things with a Layered Architecture | Jan 3, 2023 | High-Level SynthesisManagement | —Unverified | 0 | 0 |
| Software-Defined FPGA Accelerator Design for Mobile Deep Learning Applications | Feb 8, 2019 | Deep LearningHigh-Level Synthesis | —Unverified | 0 | 0 |
