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High-Level Synthesis

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Showing 1–50 of 96 papers

TitleStatusHype
Allo: A Programming Model for Composable Accelerator DesignCode3
Fast inference of deep neural networks in FPGAs for particle physicsCode2
HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and BeyondCode2
HLSTransform: Energy-Efficient Llama 2 Inference on FPGAs Via High Level SynthesisCode2
Understanding the Potential of FPGA-Based Spatial Acceleration for Large Language Model InferenceCode2
SynthAI: A Multi Agent Generative AI Framework for Automated Modular HLS Design GenerationCode1
LL-GNN: Low Latency Graph Neural Networks on FPGAs for High Energy PhysicsCode1
AutoPhase: Compiler Phase-Ordering for High Level Synthesis with Deep Reinforcement LearningCode1
AutoPhase: Juggling HLS Phase Orderings in Random Forests with Deep Reinforcement LearningCode1
rule4ml: An Open-Source Tool for Resource Utilization and Latency Estimation for ML Models on FPGACode1
Design and Implementation of an FPGA-Based Hardware Accelerator for TransformerCode1
LeFlow: Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural NetworksCode1
GenGNN: A Generic FPGA Framework for Graph Neural Network AccelerationCode1
DGNN-Booster: A Generic FPGA Accelerator Framework For Dynamic Graph Neural Network InferenceCode1
GNNHLS: Evaluating Graph Neural Network Inference via High-Level SynthesisCode1
Edge-MoE: Memory-Efficient Multi-Task Vision Transformer Architecture with Task-level Sparsity via Mixture-of-ExpertsCode1
Accelerating Recurrent Neural Networks for Gravitational Wave ExperimentsCode1
Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNsCode1
HLS-Eval: A Benchmark and Framework for Evaluating LLMs on High-Level Synthesis Design TasksCode1
A scalable and efficient convolutional neural network accelerator using HLS for a System on Chip designCode1
PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNsCode1
Towards a Comprehensive Benchmark for High-Level Synthesis Targeted to FPGAsCode1
LLM-DSE: Searching Accelerator Parameters with LLM AgentsCode1
Exploring Code Language Models for Automated HLS-based Hardware Generation: Benchmark, Infrastructure and Analysis—0
Face Recognition with Hybrid Efficient Convolution Algorithms on FPGAs—0
FFCNN: Fast FPGA based Acceleration for Convolution neural network inference—0
Firmware implementation of a recurrent neural network for the computation of the energy deposited in the liquid argon calorimeter of the ATLAS experiment—0
FPGA-Based CNN Inference Accelerator Synthesized from Multi-Threaded C Software—0
FPGA-Based Hardware Accelerator of Homomorphic Encryption for Efficient Federated Learning—0
Enabling Automated FPGA Accelerator Optimization Using Graph Neural Networks—0
Gradient Backpropagation based Feature Attribution to Enable Explainable-AI on the Edge—0
HENNC: Hardware Engine for Artificial Neural Network-based Chaotic Oscillators—0
High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing—0
Sensor Signal Processing using High-Level Synthesis and Internet of Things with a Layered Architecture—0
Accelerating Markov Random Field Inference with Uncertainty Quantification—0
A Compilation Flow for the Generation of CNN Inference Accelerators on FPGAs—0
A Graph Deep Learning Framework for High-Level Synthesis Design Space Exploration—0
A reconfigurable neural network ASIC for detector front-end data compression at the HL-LHC—0
A Reconfigurable Stream-Based FPGA Accelerator for Bayesian Confidence Propagation Neural Networks—0
Are LLMs Any Good for High-Level Synthesis?—0
A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures—0
A system on chip for melanoma detection using FPGA-based SVM classifier—0
AutoHLS: Learning to Accelerate Design Space Exploration for HLS Designs—0
Automated C/C++ Program Repair for High-Level Synthesis via Large Language Models—0
Automatic Optimization of Hardware Accelerators for Image Processing—0
Brain-Inspired Deep Networks for Image Aesthetics Assessment—0
Can Reasoning Models Reason about Hardware? An Agentic HLS Perspective—0
Chimera: A Hybrid Machine Learning Driven Multi-Objective Design Space Exploration Tool for FPGA High-Level Synthesis—0
Code Generation for High-Level Synthesis of Multiresolution Applications on FPGAs—0
Cross-Modality Program Representation Learning for Electronic Design Automation with High-Level Synthesis—0
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