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High-Level Synthesis

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Showing 1–50 of 96 papers

TitleStatusHype
Iceberg: Enhancing HLS Modeling with Synthetic DataCode0
Embedded FPGA Acceleration of Brain-Like Neural Networks: Online Learning to Scalable Inference—0
iDSE: Navigating Design Space Exploration in High-Level Synthesis Using LLMs—0
LLM-DSE: Searching Accelerator Parameters with LLM AgentsCode1
Intelligent4DSE: Optimizing High-Level Synthesis Design Space Exploration with Graph Neural Networks and Large Language Models—0
HLS-Eval: A Benchmark and Framework for Evaluating LLMs on High-Level Synthesis Design TasksCode1
Enhancing CuFP Library with Self-Alignment TechniqueCode0
Design and Implementation of an FPGA-Based Hardware Accelerator for TransformerCode1
Can Reasoning Models Reason about Hardware? An Agentic HLS Perspective—0
A Reconfigurable Stream-Based FPGA Accelerator for Bayesian Confidence Propagation Neural Networks—0
Exploring Code Language Models for Automated HLS-based Hardware Generation: Benchmark, Infrastructure and Analysis—0
MetaML-Pro: Cross-Stage Design Flow Automation for Efficient Deep Learning Acceleration—0
Neural Architecture Codesign for Fast Physics ApplicationsCode0
Intelligent experiments through real-time AI: Fast Data Processing and Autonomous Detector Control for sPHENIX and future EIC detectors—0
Agentic-HLS: An agentic reasoning based high-level synthesis system using large language models (AI for EDA workshop 2024)Code0
KALAM: toolKit for Automating high-Level synthesis of Analog computing systeMs—0
Hierarchical Mixture of Experts: Generalizable Learning for High-Level SynthesisCode0
Learning to Compare Hardware Designs for High-Level SynthesisCode0
Are LLMs Any Good for High-Level Synthesis?—0
Efficient Task Transfer for HLS DSE—0
rule4ml: An Open-Source Tool for Resource Utilization and Latency Estimation for ML Models on FPGACode1
HENNC: Hardware Engine for Artificial Neural Network-based Chaotic Oscillators—0
Exploring the Limitations of Kolmogorov-Arnold Networks in Classification: Insights to Software Training and Hardware ImplementationCode0
CuFP: An HLS Library for Customized Floating-Point OperatorsCode0
Deep Inverse Design for High-Level SynthesisCode0
Automated C/C++ Program Repair for High-Level Synthesis via Large Language Models—0
New Solutions on LLM Acceleration, Optimization, and Application—0
Cross-Modality Program Representation Learning for Electronic Design Automation with High-Level Synthesis—0
fSEAD: a Composable FPGA-based Streaming Ensemble Anomaly Detection LibraryCode0
SynthAI: A Multi Agent Generative AI Framework for Automated Modular HLS Design GenerationCode1
Fast Algorithms for Spiking Neural Network Simulation with FPGAsCode0
HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and BeyondCode2
HLSTransform: Energy-Efficient Llama 2 Inference on FPGAs Via High Level SynthesisCode2
Skip the Benchmark: Generating System-Level High-Level Synthesis Data using Generative Machine LearningCode0
Allo: A Programming Model for Composable Accelerator DesignCode3
AutoHLS: Learning to Accelerate Design Space Exploration for HLS Designs—0
Subgraph Extraction-based Feedback-guided Iterative Scheduling for HLS—0
Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNsCode1
Understanding the Potential of FPGA-Based Spatial Acceleration for Large Language Model InferenceCode2
A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures—0
Leveraging High-Level Synthesis and Large Language Models to Generate, Simulate, and Deploy a Uniform Random Number Generator Hardware Design—0
Implementation of hyperspectral inversion algorithms on FPGA: Hardware comparison using High Level Synthesis—0
GNNHLS: Evaluating Graph Neural Network Inference via High-Level SynthesisCode1
Towards a Comprehensive Benchmark for High-Level Synthesis Targeted to FPGAsCode1
SEER: Super-Optimization Explorer for HLS using E-graph Rewriting with MLIR—0
INR-Arch: A Dataflow Architecture and Compiler for Arbitrary-Order Gradient Computations in Implicit Neural Representation ProcessingCode0
Edge-MoE: Memory-Efficient Multi-Task Vision Transformer Architecture with Task-level Sparsity via Mixture-of-ExpertsCode1
ProgSG: Cross-Modality Representation Learning for Programs in Electronic Design Automation—0
DGNN-Booster: A Generic FPGA Accelerator Framework For Dynamic Graph Neural Network InferenceCode1
DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators—0
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