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High-Level Synthesis

Papers

Showing 125 of 96 papers

TitleStatusHype
Allo: A Programming Model for Composable Accelerator DesignCode3
Fast inference of deep neural networks in FPGAs for particle physicsCode2
HLSTransform: Energy-Efficient Llama 2 Inference on FPGAs Via High Level SynthesisCode2
Understanding the Potential of FPGA-Based Spatial Acceleration for Large Language Model InferenceCode2
HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and BeyondCode2
SynthAI: A Multi Agent Generative AI Framework for Automated Modular HLS Design GenerationCode1
rule4ml: An Open-Source Tool for Resource Utilization and Latency Estimation for ML Models on FPGACode1
LL-GNN: Low Latency Graph Neural Networks on FPGAs for High Energy PhysicsCode1
Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNsCode1
GenGNN: A Generic FPGA Framework for Graph Neural Network AccelerationCode1
LLM-DSE: Searching Accelerator Parameters with LLM AgentsCode1
PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNsCode1
GNNHLS: Evaluating Graph Neural Network Inference via High-Level SynthesisCode1
Towards a Comprehensive Benchmark for High-Level Synthesis Targeted to FPGAsCode1
AutoPhase: Compiler Phase-Ordering for High Level Synthesis with Deep Reinforcement LearningCode1
Design and Implementation of an FPGA-Based Hardware Accelerator for TransformerCode1
Accelerating Recurrent Neural Networks for Gravitational Wave ExperimentsCode1
AutoPhase: Juggling HLS Phase Orderings in Random Forests with Deep Reinforcement LearningCode1
DGNN-Booster: A Generic FPGA Accelerator Framework For Dynamic Graph Neural Network InferenceCode1
Edge-MoE: Memory-Efficient Multi-Task Vision Transformer Architecture with Task-level Sparsity via Mixture-of-ExpertsCode1
LeFlow: Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural NetworksCode1
HLS-Eval: A Benchmark and Framework for Evaluating LLMs on High-Level Synthesis Design TasksCode1
A scalable and efficient convolutional neural network accelerator using HLS for a System on Chip designCode1
AutoHLS: Learning to Accelerate Design Space Exploration for HLS Designs0
A system on chip for melanoma detection using FPGA-based SVM classifier0
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