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Showing 976–1000 of 2231 papers

TitleStatusHype
DyNet: Dynamic Convolution for Accelerating Convolution Neural Networks—0
GHOST: A Graph Neural Network Accelerator using Silicon Photonics—0
Benchmarking Edge AI Platforms for High-Performance ML Inference—0
Cross-Stack Workload Characterization of Deep Recommendation Systems—0
Joint Optimization of the Deployment and Resource Allocation of UAVs in Vehicular Edge Computing and Networks—0
Hierarchical Federated Learning in Wireless Networks: Pruning Tackles Bandwidth Scarcity and System Heterogeneity—0
DynaSplit: A Hardware-Software Co-Design Framework for Energy-Aware Inference on Edge—0
Dynamic Vision Sensor integration on FPGA-based CNN accelerators for high-speed visual classification—0
Global Neighbor Sampling for Mixed CPU-GPU Training on Giant Graphs—0
GnetDet: Object Detection Optimized on a 224mW CNN Accelerator Chip at the Speed of 106FPS—0
GnetSeg: Semantic Segmentation Model Optimized on a 224mW CNN Accelerator Chip at the Speed of 318FPS—0
Heterogeneous Acceleration Pipeline for Recommendation System Training—0
Dynamic Transformer for Efficient Machine Translation on Embedded Devices—0
Dynamic Superblock Pruning for Fast Learned Sparse Retrieval—0
A Multi-Agent System Approach to Load-Balancing and Resource Allocation for Distributed Computing—0
HFL: Hybrid Fuzzing on the Linux Kernel—0
Google Coral-based edge computing person reidentification using human parsing combined with analytical method—0
GossipGraD: Scalable Deep Learning using Gossip Communication based Asynchronous Gradient Descent—0
GPGPU Acceleration of the KAZE Image Feature Extraction Algorithm—0
A General Framework for Constrained Bayesian Optimization using Information-based Search—0
GPTVQ: The Blessing of Dimensionality for LLM Quantization—0
CWD: A Machine Learning based Approach to Detect Unknown Cloud Workloads—0
GPU Accelerated Cascade Hashing Image Matching for Large Scale 3D Reconstruction—0
AMPLE: Event-Driven Accelerator for Mixed-Precision Inference of Graph Neural Networks—0
Accelerating Framework of Transformer by Hardware Design and Model Compression Co-Optimization—0
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