VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verification

Code

• github.com/wilyub/verithoughts
  OfficialIn paperpytorch★ 21

Abstract

This paper introduces VeriThoughts, a novel dataset designed for reasoning-based Verilog code generation. We establish a new benchmark framework grounded in formal verification methods to evaluate the quality and correctness of generated hardware descriptions. Additionally, we present a suite of specialized small-scale models optimized specifically for Verilog generation. Our work addresses the growing need for automated hardware design tools that can produce verifiably correct implementations from high-level specifications, potentially accelerating the hardware development process while maintaining rigorous correctness guarantees. Our code and data are available at this URL.

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Reproductions