An improved wavelet-based signal-denoising architecture with less hardware consumption

Abstract

This paper introduces a wavelet denoising architecture with adaptive thresholding for real-time 1D-systems and without the use of external memories for storing input data or wavelet coefficients. The Discrete Wavelet Transform (DWT) is executed sample-by-sample by a polyphase scheme of the biorthogonal base 5/3. Since the weights of the filters are represented by integer terms and the quantization error is quasi-zero, the principle of Perfect Reconstruction is satisfied. The adaptive threshold is based on a real-time sorting process which calculates the median of the detail coefficients. Simulations are presented to measure the delay, latency, quantization error and hardware cost. A comparison with related works is also provided in order to show the strengths of the current proposal. The good trade-off among reconstruction error, latency, delay and hardware cost permits to use the proposed architecture in a wide variety of signals that require good fidelity and prompt response. In this paper, we propose the VLSI implementation of a wavelet packet transform-based architecture. Moreover, the proposed architecture is compared to the wavelet transform architecture in terms of their signal denoising capabilities, hardware resources used, maximum operating frequency and maximum combination path delay. The Wavelet packet transform architecture is designed and implemented for db2 and db3 wavelet types. For the proposed real-time VLSI implementation, the Xilinx Spartan-6 series FPGA platform is used. Simulation results show that the proposed architecture implementation results in an improved performance for ECG signals taken from the Fantasia Database as well as from the self-recorded database, as compared to the WT wavelet architectures which result in distorted outputs. Moreover, from the synthesis results, it is concluded that the proposed architecture implementation requires significantly less hardware as compared to the WT architectures considered. In terms of LUTs, the proposed architecture consumes 38.20 percent and 84.96 percent less resources than the WT-db2 and WT-db5 architectures, respectively. Similarly, in terms of slice registers, the proposed architecture consumes, respectively, 21.39 percent and 75.61 percent less resources than the WT-db2 and WT-db5 architectures. Furthermore, the maximum operating frequency of the proposed architecture is 180.278 MHz as compared to that of 195.496 MHz and 121.038 MHz for the WT-db2 and WT-db5 architectures respectively. The maximum combinational path delay of the proposed architecture is 48.109 ns, as compared to that of 13.784 ns and 15.202 ns for the WT-db2 and WT-db5 architectures, respectively.

Tasks

Reproductions